A semiconductor device is manufactured by repeating the process of transferring a pattern to a wafer with a photo mask by lithographic and etching techniques. Between the manufacturing stages, ion implantation takes place to form PN junctions. The processing quality in the various steps of the semiconductor device manufacturing process, including a lithographic processing step, an etching step and an ion implantation step, considerably influences the semiconductor device yield rate. Therefore, in order to improve the yield rate, it is important to early detect or predict any defects and the types of defects so as to feedback the manufacturing condition data.
A particularly important thing in the above-mentioned defect detection process is to detect such defects as via (or contact) hole incomplete contact defects, short-circuit defects, and defects in PN junctions at the bottom of via (or contact) holes. In order to know the type of defect, it is necessary to measure the resistance at a desired voltage. Also, in order to identify the cause of a defect, it is important to measure resistances over a range of voltages. The following two conventional techniques have been used to make such measurements.
One method uses a nano-prober (JP-A-160109/1996). In this method, current-voltage characteristics are measured by bringing a sharp W probe (approx. 0.1 μm point curvature radius) into contact with the sample to apply a voltage to the sample thereby measuring the current flowing between the sample and the probe. However, with the growing trend toward finer patterns, the area to be measured tends to be as small as or smaller than the W probe, which makes measurement very difficult. A possible solution to this problem may be the use of a W probe with a smaller point curvature radius. However, this approach is not realistic because the point is very soft and may deform upon contact with the object or sample. In addition, there are three other problems. The first problem is that if the probe and the sample are made of different materials, particularly at least one of them is a semiconductor, a Schottky junction may occur and a voltage-dependent electric resistance may be generated, which causes incorrect measurements. Secondly, this approach is not suitable for the whole wafer surface because of its slow measuring speed. Thirdly, because the probe touches the sample, the wafer may be contaminated such that the approach is not suitable for an in-line inspection.
Another method is the use of an SEM (scanning electron microscope). The method is disclosed in JP-A-258703/1993, JP-A-121561/1999, proceedings No.2 of the 61st Meeting of the Japan Society of Applied Physics (p.671, 3p-K-4), and the Proceedings of SPIE Vol. 4344 (2001) p.12.
JP-A-258703/1993 discloses a method by which a voltage contrast image of a pattern on a wafer which is obtained using an SEM is compared with that of an adjacent pattern to decide where there is a defect with a different voltage contrast (brightness). Although this inspection method is speedy and suitable for whole wafer surface inspection, a brightness difference between voltage contrast images only suggests a difference in electric resistance and no quantitative data is obtained from this inspection. In addition, depending on the orientation of a PN junction, the junction part, when electrically charged, may have a high resistance, such that it is difficult to determine whether or not there is an incomplete contact defect.
JP-A-121561/1999 discloses a method by which the emission of secondary electrons is controlled by a control electrode in front of a wafer to charge the wafer surface positively or negatively. Whether or not there is a defect is determined from a corresponding voltage contrast image. How the emission of secondary electrons is controlled by the control electrode is disclosed in JP-A-155941/1984. According to JP-A-121561/1999, if the control electrode is adjusted so as to positively charge the wafer, the low-resistance portion of the voltage contrast image is bright and its high-resistance portion is dark; and vice versa (if the wafer is negatively charged.) Although this inspection method is speedy and suitable for whole wafer surface inspection, whether each of the voltage contrast image portions is bright or dark merely suggests whether the resistance is high or low, and the relationship between image brightness and resistance is not indicated quantitatively such that resistance values cannot be calculated. Therefore, it is impossible to confirm, for example, whether the reverse bias resistance value of a PN junction is correct or not. Also this prior art claims that the positively or negatively charged wafer condition can be used to identify the orientation of a PN junction; however, if a highly electrically charged condition is produced by electron beam irradiation, the junction might break down with a resulting drastic drop in resistance. The prior art can not identify the orientation of a PN junction which makes the inspection impossible. According to this prior art, this problem is unavoidable because the charged voltage cannot be measured. Besides, although electric resistances can be calculated by measuring leak currents, it takes time to make such an inspection such that the measurement cannot be made quickly.
A method for calculating electric resistances from voltage contrast image signals is disclosed in p.671, 3p-K-4 of proceedings No.2 of the 61st Meeting of the Japan Society of Applied Physics and the Proceedings of SPIE Vol. 4344 (2001) p.12. The resistance-voltage calculation would be impossible with the prior art described in JP-A-258703/1993 or JP-A-121561/1999. However, this method focuses on inspection under a positively charged condition and no reference is made to inspection under a negatively charged condition. Furthermore, even under a positively charged condition, only the resistance at a specific voltage can be measured but the specific voltage is unknown. Therefore, it is impossible to calculate the resistance-voltage characteristics of an electronic device such that it is difficult to identify the type of defect. Another problem is that since the charged voltage cannot be controlled and measured, a breakdown of a PN junction cannot be avoided.
On the other hand, the method which uses a nano-prober has the following problems. One is that the object to be measured may be smaller than the point of the probe. A second problem is that in some kind of sample, an electric resistance cannot be estimated accurately due to the contact resistance between the probe and the sample. Another problem is that a long inspection time is required and that the whole wafer surface inspection is impossible.
In most of the SEM-based inspection devices, a resistance value is relatively evaluated from voltage contrast image signal data. Some SEM-based devices use a method by which an electric resistance is determined from voltage contrast image signal data. However, in both methods, an inspection is made at a specific charged voltage level such that a breakdown may occur due to a high electrostatic with a resultant decline in defect detection sensitivity. Also it is impossible to calculate the electric characteristics (resistance-voltage) of an electronic device and to identify the type of defect. In another method in which resistance values are calculated by measuring leak currents, an inspection is made under a specific charged voltage condition and it takes time to make such an inspection; in other words, an inspection cannot be made quickly and the whole surface of a wafer can hardly be inspected.
The present invention has been made to solve the above problems by providing an inspection method and an inspection device which enable defect detection under a controlled charged voltage condition, permit calculation of resistance-voltage characteristics of electronic devices and quickly find out electric characteristic distribution on the whole wafer surface as well as defect distribution by type.